The present invention relates to methods and circuitry for interfacing integrated circuits to other devices within a computer system. More particularly, the invention relates to methods and circuitry by which an integrated circuit may automatically configure itself to use any one of several known interface techniques and protocols.
Many digital and analog integrated circuit devices are controlled by means of digital data which is written to or read from registers within the integrated circuit by another device. Data written to a register may specify an operational mode or configuration of the integrated circuit, for example, by selecting an input channel in an analog-to-digital converter (ADC), or by providing output information such as an output level of a digital-to-analog converter (DAC). Alternatively, the data in a register may represent a value to be read by a processor, for example, the current date and time maintained by a real time clock (RTC) integrated circuit. Still other integrated circuit devices, such as non-volatile random access memory (NVRAM), are used to provide storage for configuration information or other important data for other devices in a system even when the system itself is turned off.
Data typically is written to or read from a register of an integrated circuit device by signals passed between the integrated circuit and another device, such as a microprocessor or signal processor, in accordance with a predetermined protocol. Interface circuitry in the integrated circuit device interprets the signals according to this protocol, which defines the meaning of the various signals and the relationships between them. In systems requiring a high data bandwidth, integrated circuits are frequently designed with parallel interfaces, wherein multiple bits of data are transferred between the integrated circuit and a processor simultaneously, as part of a single transaction. However, the trend toward smaller packages and increased circuit density in electronic devices places a high premium on printed circuit board area and integrated circuit pins, and consequently, on the number of signal lines required to interface various integrated circuits to each other. Thus, parallel interfaces may not be cost effective in low data rate applications. For these and other reasons, serial interfaces and protocols have become popular methods of interconnecting integrated circuits and processors within a computer system.
Several serial protocols have been developed which address a wide range of serial interfacing needs, and which offer various trade-offs between hardware and software complexity. As in any design process, a system designer working with integrated circuit devices must balance costs and benefits when selecting the specific devices to be used in the system. One consideration in this balance is the protocol by which the devices communicate.
One known type of multi-wire serial interface protocol, commercial embodiments of which include the SPI (Motorola) and MICROWIRE (National Semiconductor) protocols, provides for synchronous, bi-directional communications between a single master device (e.g., a processor) and a selected slave device. A detailed description of the SPI interface protocol is provided in Section 6 "Serial Peripheral Interface (SPI)" of the "Motorola MC68HC11A8 Data Book," Motorola, 1988. The interface protocol uses four signals which include chip select (/CS), clock (CLK), data input (DIN), and data output (DOUT). A specific device is selected by a host processor asserting the /CS line, while pulses provided on the CLK line synchronize the transfer of data from the processor to the target device (on the DIN line), or from the device to the processor (on the DOUT line). If bi-directional communication is not required for a particular application, either the DIN or DOUT signal may be omitted, thus reducing the total number of signals required to implement the interface protocol.
The "/" symbol is used herein to indicate the logical complement of a signal. Other symbols may be seen in the art to indicate logical complement including a minus ("-") placed before a signal name, or a bar (".sup.. ") placed over the signal name. When used with the name of an input signal, such as /CS, the complement symbol indicates that the line is considered active when a low signal is placed on the line. In the drawings, this is also indicated by a small circle on the input. When the "/" symbol is used with the name of an output signal, it means that the signal is the complement of the signal having the same name without the "/" symbol. For example, the /Q output of a flip-flop is the complement of the Q output of the same flip-flop. Thus the /CS signal of the preceding paragraph is asserted by driving it low.
Another known serial interface protocol is the Inter-Integrated Circuit (I.sup.2 C) Bus protocol, which is described in detail in "Signetics Microcontroller User's Guide", 1988, pages 4-1 through 4-12. This protocol is a two wire bi-directional, synchronous serial interface between multiple integrated circuit devices. A bus master device controls the Serial CLock (SCL) line while address and data bytes are transferred on the Serial DAta (SDA) line. Unlike the SPI interface protocol, I.sup.2 C does not use a /CS line to designate the integrated circuit participating in a transaction; rather, addressing information is transmitted on the SDA line as part of the transaction. Thus devices interfaced using I.sup.2 C must have enough "intelligence" to recognize and respond when their own address is sent on the SDA line.
Microprocessors are known in which general purpose I/O pins may be configured to function as a dedicated serial port according to a predetermined protocol. For example, there is a variant of the 8051 microprocessor in which some I/O pins may be configured as an SPI port, and another variant of the 8051 microprocessor in which some I/O pins may be configured as an I.sup.2 C port. However, neither of these variants of the 8051 allows the same I/O port to be configured selectively as either an SPI or I.sup.2 C port. The I/O pins of the microprocessor are configured by programming an internal configuration register, typically during execution of start-up code following a microprocessor reset.
Both the SPI and I.sup.2 C protocols provide a host processor with a high degree of flexibility and control in communications with another integrated circuit device. However, both SPI and I.sup.2 C are relatively complex protocols and many applications are better suited for simpler, less costly, interface protocols.
One very simple serial interface protocol (the "increment-only" protocol) requires only a single signal line. The signal line is used to send clock pulses. According to this protocol, an integrated circuit contains a counter whose value is incremented by some predefined amount every time a clock pulse is received. In order to increase the value stored in the counter, a controlling processor sends an appropriate number of clock pulses to the integrated circuit. For example, to increment the counter by twelve when each clock pulse increments the counter by four, the processor sends three clock pulses to the integrated circuit.
Decrementing the counter's value is accomplished by letting the counter "roll over" from a maximum possible value, to a minimum possible value. To reduce a value stored in the counter, the processor must send a sufficient number of pulses to cause the counter to roll over, and then send the correct number of clock pulses to increment the counter to the new desired value. For a counter having many bits, a large number of pulses must be sent to the integrated circuit in order to cause the counter to roll over. If the counter has m bits, a total of 2.sup.m -1 clock pulses must be supplied to decrement the counter by one. Thus the simplicity of the interface protocol may be offset by the expense of increased complexity of the controlling software. Furthermore, because of the time needed to communicate information, this protocol may be inappropriate for "real time" applications.
Another known, relatively simple, serial interface protocol refines techniques of the increment-only protocol by introducing a direction signal, also referred to as an "increment/decrement", or "up/down", signal. As in the increment-only protocol, clock pulses sent by a processor cause a counter within the integrated circuit to change by a predetermined amount. However, the direction signal is used to indicate the direction of the change. For example a high signal on the direction line may cause the counter to increment when a clock pulse is received, whereas a low signal on the direction line causes the counter to decrement with each clock pulse. The addition of a direction signal provides a host processor with a more direct means of controlling the value of the counter within the integrated circuit, thereby simplifying the software needed to control the integrated circuit.
The protocols discussed thus far are all synchronous protocols, i.e., an action or data transfer occurs in synchronization with a pulse on a clock line. Asynchronous protocols, on the other hand, have no explicit clock signal, relying instead on special formats for framing and transmitting data to synchronize the receiving device's internal clock with that of the sending device. The widely used RS-232 protocol is one example of an asynchronous serial protocol. The advantage of an asynchronous protocol is that only one or two data lines are required, depending upon whether a bi-directional data line is used, and no explicit clock signal is required. These characteristics make asynchronous protocols better suited for long distance communications in which providing a clock signal line requires considerable expense.
Each of the protocols described herein has associated limitations and drawbacks which must be taken into account when an electronic system, such as a computer or embedded control system, is being designed. The design process, which involves balancing the trade-offs among different competing designs, is frequently an iterative process, possibly requiring a system designer to switch from one protocol to another when designing the interface between a processor and a supporting integrated circuit device. For example, in a system using an SPI interface protocol to communicate with a DAC, the addition of a new feature to the system may require the dedicated use of another processor I/O pin. If no more I/O pins are available, the designer may have to add an external register to increase the number of I/O pin available to the microprocessor. Historically, this has been the most common technique, since the desired peripheral functions are generally not available with a variety of interface protocols. If adding an external register is not a desirable design choice, the designer may be forced to switch to an "up/down" style interface protocol between the processor and the DAC in order to make a pin available. Currently, such a design change requires the designer to replace the DAC supporting the SPI protocol with a different DAC which supports the up/down protocol. Often, the pin configuration of the new DAC using the up/down protocol differs from the previous DAC which used the SPI protocol, thus necessitating a re-layout of the printed circuit board, as well as other potential changes to the system design.
Additionally, to offer its customers a variety of interface options integrated circuit manufacturers must provide multiple versions of an integrated circuit design, each version supporting one of the interface protocols. This leads to a proliferation of integrated circuit devices having similar functionality, but each having a unique part number. Thus a customer must be familiar with the variations of each design and must purchase and inventory a large number of unique parts. Likewise, manufacturers must maintain an inventory of many unique parts, resulting in increased costs.
In view of the foregoing it would be desirable to be able to provide in an integrated circuit, interface circuitry which can be configured to use any one of several different interface protocols, so that the same integrated circuit may be used regardless of which interface protocol is selected.
It would further be desirable to be able to provide in an integrated circuit, interface circuitry which is configurable to operate in accordance with any one of several protocols without adding pins solely for the purpose of configuring the interface.
It would also be desirable to be able to provide in an integrated circuit, interface circuitry which automatically configures itself to use a particular protocol in response to signals received from a host device.
It would, in addition, be desirable to be able to provide in an integrated circuit, interface circuitry which automatically configures itself to use a particular protocol in response to the use of the particular protocol by a master device or processor.